Electronic design automation (EDA) is a category of software systems for assisting with the design of electronic systems and devices. Timing analysis is an EDA function for analyzing timing of circuit elements and/or circuit blocks to verify whether a digital circuit meets expected constraints and operational clock rates.
As part of timing analysis, static timing analysis (STA) uses models that describe characteristics of a digital circuit (e.g., library models, parasitic models, timing derates, standard delay format, system constraints, delay calculation, slack, timing reports, and multimode multi-corner analysis) to compute an expected time of the digital circuit and to do so without requiring simulation of the entire digital circuit, which can be resource intensive. A design team generally uses STA to determine whether various clocks and signals within a circuit design are correctly implemented, which can determine whether a circuit will operate as planned or even function.
STA is usually performed over a set of varying conditions (e.g., temperature variations, voltage variations, parameters for a resistor-capacitor [RC] reduction) and determines best- and worst-case timing delays of the digital circuit independent of its inputs (e.g., based on interference effects of neighboring aggressor nets on victim nets). Analyzing a circuit design under a given set of conditions may be defined by a view. An example view can include, without limitation, an RC corner identifying a set of parameters for RC reduction, a library file, a mode for simulating a condition (e.g., low-power or high-temperature condition), or a case selection (e.g., maximum delay, minimum delay, average delay, etc.).
Before a circuit design tapeout, STA is usually performed on a design multiple times (i.e., multiple STA runs) until timing signoff verification is achieved. Some of these STA runs can be performed within a single analysis session with some changes to either settings or constraints, or by application of engineering change orders (ECOs) (e.g., an ECO to fix a timing violation or a design rule violation [DRV]), all of which may impact a small section of the circuit design from a timing delay perspective.
Unfortunately, timing signoff can be a time-consuming exercise during STA when a delay calculation of all the stages/nets of a digital circuit design is performed for each STA run.